1. Technical Field
The present invention relates to phase-locked loop calibration and, in particular, to phase-locked loop calibration that reduces glitch and overshoot.
2. Discussion of Related Art
Phase-Locked Loops (PLLs) find application in various contexts where a stable, often high frequency, clock signal is desired. Applications of PLLs include, for example, clock generation for CPUs and for telecommunications. Often, PLLs utilize a calibration procedure to improve the performance of the PLL. Calibration may be especially important for PLLs with large tuning ranges.
During calibration, the output signal frequency of the PLL is adjusted to a particular response to an input reference clock. During calibration code jumps, where the frequency adjustment of the PLL output signal is made, the output clock signal from the PLL may experience overshoot or glitch. If this clock signal is then used as the system clock in a particular chip, the overshoot or glitch can induce computational error or even system failure.
Overshoot usually occurs during a frequency ascending code jumping portion of the calibration procedure. During the calibration process of jumping from a calibration code that results in a low frequency output clock signal to a calibration code that results in a high frequency output clock signal, the PLL output clock signal may be momentarily at a higher frequency than the system can accommodate, so overshoot occurs. In some cases, a frequency descending code can be utilized during the calibration procedure to avoid overshoot because the frequency then changes from high frequency to low frequency clock signals during the calibration process. However, even a frequency descending code sequence has a risk of overshoot if a calibration process is needed at any moment during a work state, which happens, for example, if the input reference clock to the PLL changes suddenly. In a descending frequency calibration sequence, the calibration code jumps from the current code to the highest frequency code in order to start the descending code sequence. During the initial transition to the calibration code resulting in the highest frequency output clock signal, overshoot may occur.
Glitch can also occur during calibration code jumps. Usually, the calibration acts on delay cells of a voltage-controlled oscillator (VCO) of the PLL (e.g. by switching the capacitances on delay cells). During switching, the switch noise can induce glitch, especially for a single end VCO.
Therefore, there is a need for a calibration for phase-locked-loops that reduces or avoids glitch or overshoot.